module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
); 

    wire	[4:0]	d;
    
    assign d[4] = q[0] ^ 1'b0;
    assign d[3] = q[4];
    assign d[2] = q[3] ^ q[0];
    assign d[1] = q[2];
    assign d[0] = q[1];
    
    always @(posedge clk) begin
        if(reset) begin
            q <= 5'h1;
        end
        else begin
            q <= d;
        end
    end
    
endmodule
